Carrier mobility in field effect transistors has been hampered by the nature of the interface between the gate dielectric layer and the underlying silicon substrate or channel. As device size has decreased, the need for higher capacitance at the transistor gate has increased. This need has been met by increasing the gate dielectric constant by introducing nitrogen into the gate oxide to form a silicon oxy-nitride compound. This nitridation of the gate dielectric may be carried out as a plasma process, and is followed by a post-nitridation anneal step to stabilize the nitrogen distribution in the gate dielectric. After gate formation, dopant impurities are implanted in source and drain regions adjacent the gate. The implanted dopants are activated in a millisecond laser annealing process in which laser radiation raises the local wafer surface temperature to melting for an extremely short period of time, using temperature ramp rates on the order of a million degrees C. per second. A type of millisecond laser annealing process known as dynamic surface annealing (DSA) is described by Jennings et al. in U.S. Pat. No. 6,987,240, the disclosure of which is incorporated herein by reference in its entirety. In the DSA process, a laser beam combined from an array of CW lasers is scanned across the wafer surface.
One problem is that the carrier mobility in the source-drain channel of the transistor is limited and needs to be improved. It is felt this limitation arises at least in part from the presence of defects or fixed charge in the dielectric at the gate dielectric-silicon channel interface. Measurements of defect density in the gate dielectric-silicon interface indicate a marked increase in defects after millisecond laser annealing or dynamic surface annealing of the implanted dopants forming the source and drain regions. It is a discovery of the present inventors that the carrier mobility-degrading defects become an embedded permanent feature of the gate dielectric-silicon interface because of two aspects of the post-implant dynamic surface anneal step. First, the peak temperature of the dynamic surface anneal process, e.g., 1300 degrees C., is hundreds of degrees above the highest temperature to which the gate dielectric-silicon interface has been subjected during any prior processing step. Secondly, the dynamic surface anneal step ramps up the local surface temperature to the silicon melting temperature and then ramps it back down to ambient at such high ramping rates (e.g., one million degrees C. per second) that there is no opportunity for gate dielectric-silicon interface defects in the gate dielectric to be annealed or cured, but instead are fixed in place (“quenched”) upon the rapid temperature ramp-down. The extreme temperature ramp rates of the dynamic surface anneal process cannot be reduced because they are necessary to avoid diffusion of the implanted dopant profile during post-implant anneal. Therefore, there is a need to improve carrier mobility in the transistor source-drain channel by avoiding effects of defects in the gate oxide at the gate dielectric-silicon interface without altering the high ramp rates of the dynamic surface anneal process.